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1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks
2.3. Address Clock Enable Support
2.4. Asynchronous Clear and Synchronous Clear
2.5. Memory Blocks Error Correction Code (ECC) Support
2.6. Agilex™ 7 Embedded Memory Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations
2.8. Force-to-Zero
2.9. Coherent Read Memory
2.10. Freeze Logic
2.11. True Dual Port Dual Clock Emulator
2.12. Initial Value of Read and Write Address Registers
2.13. Timing/Power Optimization Feature in M20K Blocks
2.14. Agilex™ 7 Supported Embedded Memory IPs
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. M20K Embedded Memory Block Input Clock Quality Requirement
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.4.5. Shift Register Ports and Parameters Setting
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4.3.1. Release Information for FIFO Intel® FPGA IP
Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.2.1 |
Quartus® Prime Version | 19.3 |
Release Date | 2019.09.30 |