Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 10/19/2023
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3.3.2. Mixed-Port Read-During-Write Mode

The mixed-port read-during-write mode applies to simple dual-port RAM mode, true dual-port, and simple quad-port RAM. Two ports perform read and write operations on the same memory address using the same clock: one port reading from the address, and the other port writing to it.
Table 15.  Output Modes for RAM in Mixed-Port Read-During-Write Mode
Output Mode Memory Type Description Supported Operation Mode
New Data MLAB

A read-during-write operation to different ports causes the MLAB registered output to reflect the New Data on the next rising edge after the data is written to the MLAB memory.

This mode is available only if the output is registered.

  • Simple Dual-port RAM
Old Data M20K, MLAB

A read-during-write operation to different ports causes the RAM output to reflect the Old Data value at that particular address.

For MLAB, this mode is available only if the output is registered.

  • Simple Dual-port RAM
Don't Care M20K, MLAB

The RAM produces Don't Care or Unknown value.

  • For M20K, the Intel® Quartus® Prime software does not analyze the timing between write and read operations.
  • For MLAB, to enable this feature, you must include the RDW_DONT_CARE_IS_X define flag in the simulation command when compiling the embedded memory simulation model and when running the simulation.
    The following is an example of adding the define flag into the simulation command:
    vlog -sv -timescale 1ps/1ps +define+RDW_DONT_CARE_IS_X -work msim_precompile $env(QUARTUS_DIR)/eda/sim_lib/altera_lnsim.sv
  • Simple Dual-port RAM
  • True Dual-port RAM (for M20K only)
New_a_old_b M20K The read-during-write operation to different ports causes the RAM output to reflect new data at port A and old data at port B.
  • Quad-port RAM
Table 16.  Mixed Port Read-During-Write Output BehaviorsThis table lists and describes the output behaviors of the mixed-port read-during-write mode. These behaviors are applicable only for MLAB blocks.
RAM: 2-PORT Intel® FPGA IP Settings Output Behavior
Parameter Enabled Parameter Options altera_syncram Parameter

(read_during_write_mode_mixed_ ports)

Output Data when Read-During-Write MLAB Atom (visible in Chip Planner)
Mixed Port Read-During-Write for Single Input Clock RAM

How should the q_a and q_b outputs behave when reading a memory location that is being written from the other ports?

Old Data old_data Old data 4 New Data
New Data new_data New data New Data
Don't Care dont_care Don't care 5 Don't Care
Figure 24. Mixed-Port Read-During-Write: New Data ModeThis figure shows a sample functional waveform of mixed-port read-during-write behavior for the New Data mode.


Figure 25. Mixed-Port Read-During-Write: Old Data ModeThis figure shows a sample functional waveform of mixed-port read-during-write behavior for the Old Data mode.


Figure 26. Mixed-Port Read-During-Write: Don't Care ModeThis figure shows a sample functional waveform of mixed-port read-during-write behavior for the Don't Care mode. This behavior is only applicable for M20K blocks.


Figure 27. Mixed-Port Read-During-Write: New_a_old_b ModeThis figure shows a sample functional waveform of mixed-port read-during-write behavior for the New_a_old_b mode.
4 Old data is achieved through external soft logic as the MLAB blocks only natively supports new data.
5 The output data is don't care because the IP does not guarantee metastability for the output data when read-during-write.