Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 10/19/2023
Public
Document Table of Contents

3.10. M20K Embedded Memory Block Input Clock Quality Requirement

A stable input clock to the selected memory block is important to ensure the success of your Intel Agilex® 7 Embedded Memory designs.
  • Ensure the input clocks are clean and stable before configuring your device. The use of PLL-generated clocks for a clean clock source is always recommended.
  • Ensure a synchronous clock switchover between clock sources by using the clock gating features available in Embedded Memory or Clock Control IP.
  • When reconfiguring the clock source in user mode, it is recommended to disable the clock enable port until the input clock is clean and stable.

For more information on optimal clocking performance, please refer to Optimizing Clocking Schemes in the Intel Quartus Prime Pro Edition User Guide: Design Recommendations and Intel Agilex® 7 Clocking and PLL User Guide for clocking and PLL design guidelines.