4.3.15. Guidelines for Embedded Memory ECC Feature
The Intel Agilex® 7 FIFO Intel® FPGA IP cores support embedded memory ECC for M20K memory blocks. The built-in ECC feature in the Intel Agilex® 7 devices can perform:
- Single-error detection and correction
- Double-adjacent-error detection and correction
- Triple-adjacent-error detection
You can turn on FIFO Embedded ECC feature by enabling enable_ecc parameter in the FIFO Intel® FPGA IP GUI.
When you enable the ECC feature, a 2-bit wide error correction status port (eccstatus[1:0]) is created in the generated FIFO entity. These status bits indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit.
- 00: No error
- 01: Illegal
- 10: A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated.
- 11: An uncorrectable error occurred and uncorrectable data appears at the output