Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 10/19/2023
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3.1. Consider the Memory Block Selection

The Intel® Quartus® Prime software automatically partitions user-defined memory into the embedded memory blocks based on the speed of your design and size constraints. For example, the Intel® Quartus® Prime software may spread out the memory across multiple available memory blocks to increase the performance of your design.

For the MLABs, you can implement single-port SRAM through emulation using the Intel® Quartus® Prime software. Emulation minimizes additional use of logic resources.

Because of the dual purpose architecture of the MLAB, the block has only data input registers, output registers, and write address registers. The MLABs gain read address registers from the ALMs.
Note: For Intel Agilex® 7 devices, the Resource Property Editor and the Timing Analyzer report the location of the M20K block as EC_X<number>_Y<number>_N<number>, even though the assigned location allowed is M20K_X<number>_Y<number>_N<number>. Embedded Cell (EC) is the sub-location of the M20K block.