Agilex™ 7 Embedded Memory User Guide

ID 683241
Date 3/29/2024
Public

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5. Agilex™ 7 Embedded Memory Debugging

Use the following guideline to help you troubleshoot common errors or issues when designing with Agilex™ 7 embedded memory.

  1. Ensure that your design does not contain any timing violation after compilation.
  2. Ensure that your design meets the recommended power specification.
  3. Debug your design using Signal Tap Logic Analyzer in the Quartus® Prime software to monitor the result of your design for random or systematic errors.
  4. Debug your design using In-System Sources and Probes in the Quartus® Prime software to control the input and monitor the result of your design.