Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/03/2023
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2.14. Fitter Settings Reference

Use Fitter settings to customize the place and route of your design. Click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) to access Fitter settings.
Table 48.  Advanced Fitter Settings (1 of 8)

Option

Description

ALM Register Packing Effort

Guides aggressiveness of the Fitter in packing ALMs during register placement. Use this option to increase secondary register locations. Increasing ALM packing density may lower the number of ALMs needed to fit the design, but it may also reduce routing flexibility and timing performance.

  • Low—the Fitter avoids ALM packing configurations that combine LUTs and registers which have no direct connectivity. Avoiding these configurations may improve timing performance but increases the number of ALMs to implement the design.
  • Medium—the Fitter allows some configurations that combine unconnected LUTs and registers to be implemented in ALM locations. The Fitter makes more use of secondary register locations within the ALM.
  • High—the Fitter enables all legal and desired ALM packing configurations. In dense designs, the Fitter automatically increases the ALM register packing effort as required to enable the design to fit.

Advanced Physical Synthesis

Enables the Physical Synthesis engine that includes combinational and sequential optimization during fitting to improve circuit performance.

Allow Delay Chains

Allows the Fitter to choose the optimal delay chain to meet tSU and tCO timing requirements for all I/O elements. Enabling this option may reduce the number of tSU violations, while introducing a minimal number of tH violations. Enabling this option does not override delay chain settings on individual nodes.

Allow DSP Retiming

Allow retiming through DSP blocks.

Allow Early Global Retiming in the Fitter

Allows the Compiler to run global retiming early in the Fitter.

Allow Hyper-Aware Register Chain Area Optimizations in the Fitter

Reduces ALM usage by automatically forcing some back-to-back registers into Hyper Registers. Turning on this area reduction technique may reduce performance and increase compile time.

Allow RAM Retiming

Allow retiming through RAM blocks.

Allow Register Duplication

Allows the Compiler to duplicate registers to improve design performance. When you enable this option, the Compiler copies registers and moves some fan-out to this new node. This optimization improves routability and can reduce the total routing wire in nets with many fan-outs. If you disable this option, this disables optimizations that retime registers.

Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Allow Register Merging

Allows the Compiler to remove registers that are identical to other registers in the design. When you enable this option, in cases where two registers generate the same logic, the Compiler deletes one register, and the remaining registers fan-out to the deleted register's destinations. This option is useful if you want to prevent the Compiler from removing intentional use of duplicate registers.

If you disable register merging, the Compiler disables optimizations that retime registers.

Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Auto Delay Chains for High Fanout Input Pins

Allows the Fitter to choose how to optimize the delay chains for high fan-out input pins. You must enable Auto Delay Chains to enable this option. Enabling this option may reduce the number of tSU violations, but the compile time increases significantly, as the Fitter tries to optimize the settings for all fan-outs.

Auto Fit Effort Desired Slack Margin

Specifies the default worst-case slack margin the Fitter maintains for. If the design is likely to have at least this much slack on every path, the Fitter reduces optimization effort to reduce compilation time.

Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Table 49.  Advanced Fitter Settings (2 of 8)

Option

Description

Auto Global Clock

Allows the Compiler to choose the global clock signal. The Compiler chooses the signal that feeds the most clock inputs to flip-flops. This signal is available throughout the device on the global routing paths. To prevent the Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to Off on that signal.

Auto Global Register Control Signals

Allows the Compiler to choose global register control signals. The Compiler chooses signals that feed the most control signal inputs to flip-flops (excluding clock signals) as the global signals. These global signals are available throughout the device on the global routing paths. Depending on the target device family, these control signals can include asynchronous clear and load, synchronous clear and load, clock enable, and preset signals. If you want to prevent the Compiler from automatically selecting a particular signal as a global register control signal, set the Global Signal option to Off on that signal.

Auto Packed Registers

Allows the Compiler to combine a register and a combinational function, or to implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option controls how aggressively the Fitter combines registers with other function blocks to reduce the area of the design. Generally, the Auto or Sparse Auto settings are appropriate.

The other settings limit the flexibility of the Fitter to combine registers with other function blocks and can result in no fits.

  • Auto—the Fitter attempts to achieve the best performance with good area. If necessary, the Fitter combines additional logic to reduce the area of the design to within the current device.
  • Sparse Auto—the Fitter attempts to achieve the highest performance, but may increase device usage without exceeding the device logic capacity.
  • Off—the Fitter does not combine registers with other functions. The Off setting severely increases the area of the design and may cause a no fit.
  • Sparse—the Fitter combines functions in a way which improves performance for many designs.
  • Normal—the Fitter combines functions that are expected to maximize design performance and reduce area.
  • Minimize Area—the Fitter aggressively combines unrelated functions to reduce the area required for placing the design, at the expense of performance.
  • Minimize Area with Chains—the Fitter even more aggressively combines functions that are part of register cascade chains or can be converted to register cascade chains.

If this option is set to any value but Off, registers combine with I/O cells to improve I/O timing. This remains true provided that the Optimize IOC Register Placement For Timing option is enabled.

Auto RAM to MLAB Conversion

Specifies whether the Fitter converts RAMs of Auto block type to use LAB locations. If this option is set to Off, only MLAB cells or RAM cells with a block type setting of MLAB use LAB locations to implement memory.

Auto Register Duplication

Allows the Fitter to automatically duplicate registers within a LAB that contains empty logic cells. This option does not alter the functionality of the design. The Compiler ignores the Auto Register Duplication option if you select OFF as the setting for the Logic Cell Insertion -- Logic Duplication logic option. Turning on this option allows the Logic Cell Insertion -- Logic Duplication logic option to improve a design's routability, but can make formal verification of a design more difficult.

Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Table 50.  Advanced Fitter Settings (3 of 8)

Option

Description

Enable Auto-Pipelining Turns on the auto-pipelining and latency-insensitive false path feature. Use this setting in conjunction with the Maximum Additional Pipelining and optional Additional Pipelining Group assignments in the Assignment Editor to automatically add pipeline registers at the locations you specify.
Note: Only available for Intel® Stratix® 10 and Intel Agilex® 7 devices.

Enable Bus-Hold Circuitry

Enables bus-hold circuitry during device operation. When this option is On, a pin retains its last logic level when it is not driven, and does not go to a high impedance logic level. Do not use this option at the same time as the Weak Pull-Up Resistor designs, enables location to the Critical Chain Viewer from the Fast option. The Compiler ignores this option if you apply it to anything other than a pin.

Enable Critical Chain Viewer

Enables critical chain visualization in the Fast Forward Timing Closure Recommendations report for Intel® Stratix® 10 and Intel Agilex® 7 devices.

Equivalent RAM and MLAB Paused Read Capabilities

Specifies whether RAMs implemented in MLAB cells must have equivalent paused read capabilities as RAMs implemented in block RAM. Pausing a read is the ability to keep around the last read value when reading is disabled. Allowing differences in paused read capabilities provides the Fitter more flexibility in implementing RAMs using MLAB cells.

To allow the Fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to Don't Care. The following options are available:
  • Don't Care—the Fitter can convert RAMs to MLAB cells, even if they do not have equivalent paused read capabilities to a block RAM implementation. The Fitter generates an information message about RAMs with different paused read capabilities.
  • Care—the Fitter does not convert RAMs to MLAB cells unless they have the equivalent paused read capabilities to a block RAM implementation.

Equivalent RAM and MLAB Power Up

Specifies whether RAMs implemented in MLAB cells must have equivalent power-up conditions as RAMs implemented in block RAM. Power-up conditions occur when the device powers-up or globally resets. Allowing non-equivalent power-up conditions provides the Fitter more flexibility in implementing RAMs using MLAB cells.

To allow the Fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to Auto or Don't Care. The following options are available:

  • Auto—the Fitter may convert RAMs to MLAB cells, even if the MLAB cells lack equivalent power-up conditions to a block RAM implementation. The Fitter also outputs a warning message about RAMs with non-equivalent power up conditions.
  • Don't Care—the same behavior as Auto applies, but the message is an information message.
  • Care—the Fitter does not convert RAMs to MLAB cells unless they have equivalent power up conditions to a block RAM implementation.

Final Placement Optimizations

Specifies whether the Fitter performs final placement optimizations. Performing final placement optimizations may improve timing and routability, but may also require longer compilation time.

Fitter Aggressive Routability Optimizations

Specifies whether the Fitter aggressively optimizes for routability. Performing aggressive routability optimizations may decrease design speed, but may also reduce routing wire usage and routing time. The Automatically setting allows the Fitter to decide whether aggressive routability is beneficial.

Table 51.  Advanced Fitter Settings (4 of 8)

Option

Description

Fitter Effort

Specifies the level of physical synthesis optimization during fitting:

  • Auto—adjusts the Fitter optimization effort to minimize compilation time, while still achieving the design timing requirements. Use the Auto Fit Effort Desired Slack Margin option to apply sufficient optimization effort to achieve additional timing margin.
  • Standard—uses maximum effort regardless of the design's requirements, leading to higher compilation time and more margin on easier designs. For difficult designs, Auto and Standard both use maximum effort.
Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Fitter Initial Placement Seed

Specifies the seed for the current design. The value can be any non-negative integer value. By default, the Fitter uses a seed of 1.

The Fitter uses the seed as the initial placement configuration when optimizing design placement to meet timing requirements fMAX. Because each different seed value results in a somewhat different fit, you can try several different seeds to attempt to obtain superior fitting results.

The seeds that lead to the best fits for a design may change if the design changes. Also, changing the seed may or may not result in a better fit. Therefore, specify a seed only if the Fitter is not meeting timing requirements by a small amount.

Note: You can also use the Design Space Explorer II (DSEII) to sweep complex flow parameters, including the seed, in the Intel® Quartus® Prime software to optimize design performance.

Logic Cell Insertion

Allows the Fitter to automatically insert buffer logic cells between two nodes without altering the functionality of the design. The Compiler creates buffer logic cells from unused logic cells in the device. This option also allows the Fitter to duplicate a logic cell within a LAB when there are unused logic cells available in a LAB. Using this option can increase compilation time. The default setting of Auto allows these operations to run when the design requires them to fit the design.
Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

MLAB Add Timing Constraints for Mixed-Port Feed-Through Mode Setting Don't Care

Specifies whether the Timing Analyzer evaluates timing constraints between the write and the read operations of the MLAB memory block. Performing a write and read operation simultaneously at the same address might result in metastability issues because no timing constraints between those operations exist by default. Turning on this option introduces timing constraints between the write and read operations on the MLAB memory block and thereby avoids metastability issues. However, turning on this option degrades the performance of the MLAB memory blocks. If your design does not perform write and read operations simultaneously at the same address, you do not need to set this option.

Number of Example Nodes Reported in Fitter Messages

Allows you to specify the maximum number of example nodes Fitter messages should display.
Table 52.  Advanced Fitter Settings (5 of 8)

Option

Description

Optimize Design for Metastability

This setting improves the reliability of the design by increasing its Mean Time Between Failures (MTBF). When you enable this setting, the Fitter increases the output setup slacks of synchronizer registers in the design. This slack can exponentially increase the design MTBF. This option only applies when using the Timing Analyzer for timing-driven compilation. Use the Timing Analyzer report_metastability command to review the synchronizers detected in your design and to produce MTBF estimates.

Optimize Hold Timing

Directs the Fitter to optimize hold time within a device to meet timing requirements and assignments. The following settings are available:

  • I/O Paths and Minimum TPD Paths—directs the Fitter to meet the following timing requirements and assignments:
    • tH from I/O pins to registers.
    • Minimum tCO from registers to I/O pins.
    • Minimum tPD from I/O pins or registers to I/O pins or registers.
  • All Paths—directs the Fitter to meet the following timing requirements and assignments:
    • tH from I/O pins to registers.
    • Minimum tCO from registers to I/O pins.
    • Minimum tPD from I/O pins or registers to I/O pins or registers.

When you disable the Optimize Timing logic option, the Optimize Hold Timing option is not available.

Optimize IOC Register Placement for Timing

Specifies whether the Fitter optimizes I/O pin timing by automatically packing registers into I/Os to minimize delays.

  • Normal—the Fitter opportunistically packs registers into I/Os that should improve I/O timing.
  • Pack All I/O Registers— the Fitter aggressively packs any registers connected to input, output, or output enable pins into I/Os, unless prevented by your constraints or other legality restrictions.
  • Off—performs no periphery to core optimization.

Optimize Multi-Corner Timing

Directs the Fitter to consider all timing corners during optimization to meet timing requirements. These timing delay corners include both fast-corner timing and slow-corner timing. By default, this option is On, and the Fitter optimizes designs considering multi-corner delays in addition to slow-corner delays. When this option is Off, the Fitter optimizes designs considering only slow-corner delays from the slow-corner timing model (slowest manufactured device for a given speed grade, operating in low-voltage conditions). Turning this option On typically creates a more robust design implementation across process, temperature, and voltage variations.

When you turn Off the Optimize Timing option, the Optimize Multi-Corner Timing option is not available.

Optimize Timing

Specifies whether the Fitter optimizes to meet the maximum delay timing requirements (for example, clock cycle time). By default, this option is set to Normal compilation. Turning this option Off helps fit designs that with extremely high interconnect requirements. Turning this option Off can also reduce compilation time at the expense of timing performance (because the Fitter ignores the design's timing requirements). If this option is Off, other Fitter timing optimization options have no effect (such as Optimize Hold Timing).

Table 53.  Advanced Fitter Settings (6 of 8)

Option

Description

Periphery to Core Placement and Routing Optimization

Specifies whether the Fitter should perform targeted placement and routing optimization on direct connections between periphery logic and registers in the FPGA core. The following options are available:

  • Auto—the Fitter automatically identifies transfers with tight timing windows, places the core registers, and routes all connections to or from the periphery. The Fitter performs these placement and routing decisions before the rest of core placement and routing. This sequence ensures that these timing-critical connections meet timing, and also avoids routing congestion.
  • On— the Fitter optimizes all transfers between the periphery and core registers, regardless of timing requirements. Do not set this option to On globally. Instead, use the Assignment Editor to assign optimization to a targeted set of nodes or entities.
  • Off—the Fitter performs no periphery to core optimization.
Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Physical Placement Effort

Controls how much effort the Fitter spends during advanced physical placement optimization. High and Maximum effort settings result in additional compile time to further optimization the placement solution.

Placement Effort Multiplier

Specifies the relative time the Fitter spends in placement. The default value is 1.0, and legal values must be greater than 0. Specifying a floating-point number allows you to control the placement effort. A higher value increases CPU time but may improve placement quality. For example, a value of '4' increases fitting time by approximately 2 to 4 times but may increase quality.

Power Optimization During Fitting

Directs the Fitter to perform optimizations targeted at reducing the total power devices consume. The available settings for power-optimized fitting are:

  • Off—performs no power optimizations.
  • Normal compilation—performs power optimizations that are unlikely to adversely affect compilation time or design performance.
  • Extra effort—performs additional power optimizations that might affect design performance or result in longer compilation time.
Table 54.  Advanced Fitter Settings (7 of 8)

Option

Description

Programmable Power Maximum High-Speed Fraction of Used LAB Tiles

Sets the upper limit on the fraction of the high-speed LAB tiles. Legal values must be between 0.0 and 1.0. The default value is 1.0. A value of 1.0 means that there is no restriction on the number of high-speed tiles, and the Fitter uses the minimum number needed to meet the timing requirements of your design. Specifying a value lower than 1.0 might degrade timing quality, because some timing critical resources might be forced into low-power mode.

Programmable Power Technology Optimization

Controls how the Fitter configures tiles to operate in high-speed mode or low-power mode. The following options are available:

  • Automatic—specifies that the Fitter minimizes power without sacrificing timing performance.
  • Minimize Power Only—specifies that the Fitter sets the maximum number of tiles to operate in low-power mode.
  • Force All Used Tiles to High Speed—specifies that the Fitter sets all used tiles to operate in high-speed mode.
  • Force All Tiles with Failing Timing Paths to High Speed—sets all failing paths to high-speed mode. For designs that meet timing, the behavior of this setting is similar to the Automatic setting.

For designs that fail timing, all paths with negative slack are put in high-speed mode. This mode likely does not increase the speed of the design, and it may increase static power consumption. This mode may assist in determining which logic paths need to be re-designed to close timing.

Note: Only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Router Timing Optimization Level

Controls how aggressively the router tries to meet timing requirements. Setting this option to Maximum can increase design speed slightly, at the cost of increased compile time. Setting this option to Minimum can reduce compile time, at the cost of slightly reduced design speed. The default value is Normal.

Table 55.  Advanced Fitter Settings (8 of 8)

Option

Description

Synchronizer Identification

Specifies how the Compiler identifies synchronization register chain registers for metastability analysis. A synchronization register chain is a sequence of registers with the same clock with no fan-out in between, which is driven by a pin or logic from another clock domain.

The following options are available:

  • Off—the Timing Analyzer does not identify the specified registers, or the registers within the specified entity, as synchronization registers.
  • Auto—the Timing Analyzer identifies valid synchronization registers that are part of a chain with more than one register that contains no combinational logic. Use the Auto setting to generate a report of possible synchronization chains in your design.
  • Forced if Asynchronous—the Timing Analyzer identifies synchronization register chains if the software detects an asynchronous signal transfer, even if there is combinational logic or only one register in the chain.
  • Forced—the Timing Analyzer identifies the specified register, or all registers within the specified entity, as synchronizers. Only apply the Forced option to the entire design. Otherwise, all registers in the design identify as synchronizers.

The Fitter optimizes the registers that it identifies as synchronizers for improved Mean Time Between Failure (MTBF), provided that you enable Optimize Design for Metastability.

If a synchronization register chain is identified with the Forced or Forced if Asynchronous option, then the Timing Analyzer reports the metastability MTBF for the chain when it meets the design timing requirements.

Treat Bidirectional Pin as Output Pin

Specifies that the Fitter treats the bidirectional pin as an output pin, meaning that the input path feeds back from the output path.

Use Checkered Pattern as uninitialized RAM Content

Loads a checkered pattern as initial RAM content into all RAM blocks without specified RAM content that supports content initialization. Turning on this option does not affect simulation, which may cause on-chip behavior to differ from simulation results.

Weak Pull-Up Resistor

Enables the weak pull-up resistor when the device is operating in user mode. This option pulls a high-impedance bus signal to VCC. Do not enable this option simultaneously with the Enable Bus-Hold Circuitry option. The Fitter ignores this option if you apply to anything other than a pin.

Other Assignments

set_global_assignment –name ERROR_ON_INVALID_ENTITY_NAME

The software ignores .qsf and .qip assignments where the entity field is not a name that exists in the design and generates a warning. If you set ERROR_ON_INVALID_ENTITY_NAME to ON, the software generates these warnings as errors.

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