Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.7. Fast Forward Compilation Flow

The Intel® Hyperflex™ architecture includes multiple Hyper-Registers in every routing segment and block input. Maximizing the use of Hyper-Registers improves the balance of time delays between registers, and mitigates critical path delays. Fast Forward compilation generates design recommendations to help you to break performance bottlenecks and maximize use of Hyper-Registers to drive the highest performance in Intel® Stratix® 10 and Intel Agilex® 7 designs.
Figure 78. Hyper-Registers in Intel® Hyperflex™ Architecture

The Fast Forward compilation reports show precisely where to make the most impact with RTL changes, and the performance benefits you can expect from each change after removing retiming restrictions. The Fast Forward compilation flow includes the following high-level steps:

Figure 79. Fast Forward Compile Flow
  1. Step 1: Run Register Retiming
  2. Step 2: Review Retiming Results
  3. Step 3: Run Fast Forward Compile
  4. Step 4: Review Fast Forward Results
  5. Step 5: Implement Fast Forward Recommendations