184.108.40.206. Running Snapshot Viewer
|Design Task||Available at Snapshot||Snapshot Viewer Commands|
|Timing Closure—Analyze Failing Paths||Planned, Placed, Routed, Finalized||
|Placed, Routed, Finalized||
|Timing Closure—Analyze Clocking
This task is available only for Intel® Stratix® 10 devices.
|Placed, Finalized||Show Global Clock Visualization—loads the Global Signal Visualization report for the snapshot that allows you to visualize clock sector utilization.|
|Timing Closure—Analyze High Fanout Nets||Placed, Routed, Finalized||
|Timing Closure—Validate Constraints||Planned||Timing Exceptions—displays the Timing Exceptions Results report that identifies timing paths with hold or removal slack exceeding threshold.|
|Planned, Placed, Finalized||Check Unregistered Ports—displays the Check Unregistered Ports Results report that identifies unregistered partition inputs and paths.|
|Timing Closure—Analyze Congestion||Placed, Routed, Finalized||Show Logic Lock Regions with Congestion Heat Map—the Chip Planner displays the Logic Lock regions in a congestion heat map for further analysis.|
The following sections describe each analysis task in detail.
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