126.96.36.199. Initial Constructs and Memory System Tasks
To avoid such errors, enclose non-synthesizable constructs (such as those intended only for simulation) in translate_off and translate_on synthesis directives. Synthesis of initial constructs enables the power-up state of the synthesized design to match the power-up state of the original HDL code in simulation.
Intel® Quartus® Prime synthesis supports the $readmemb and $readmemh system tasks to initialize memories.
Verilog HDL Code: Initializing RAM with the readmemb Command
reg [7:0] ram[0:15]; initial begin $readmemb("ram.txt", ram); end
When creating a text file to use for memory initialization, specify the address using the format @<location > on a new line, and then specify the memory word such as 110101 or abcde on the next line.
The following example shows a portion of a Memory Initialization File (.mif) for the RAM.
Text File Format: Initializing RAM with the readmemb Command
@0 00000000 @1 00000001 @2 00000010 … @e 00001110 @f 00001111