2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
2.4.2. Viewing Synthesis Reports
The Compilation Report window opens automatically during compilation processing. The Report window displays detailed synthesis results for each partition in the current project revision.
Figure 49. Synthesis Reports
|Summary||Shows summary information about synthesis, such as the status, date, software version, entity name, device family, timing model status, and various types of logic utilization.|
|Settings||Lists the values of all synthesis settings during design processing.|
|Source Files Read||Lists details about all source files in design synthesis. Details include file path, file type, and any library information.|
|IP Cores Summary||Lists details about each IP core instance in design synthesis. Details include IP core name, vendor, version, license type, entity instance, and IP include file.|
|Partition Summary||Shows a summary of partitions in the design. Details include partitions names, hierarchy path, partition type, and partition properties.|
|Source Assignments||A series of reports that list details about source assignments. Details include assignment, value, and source location.|
|Parameter Settings by Entity Instance||A series of reports that list parameter settings for entities in your design. Details in the reports include parameter name, parameter value, and parameter data type.|
|Partition reports||Each design partition has a series of reports:
Lists all information, warning, and error messages that report conditions observed during the Analysis & Synthesis process.
|Warning Messages||A series of reports that summarize the warning messages generated during synthesis by providing one entry per message ID, its severity, the count of all its occurrences, and one sample warning message.
A separate report is generated for warnings from each source file. General warning messages that are not associated with a source file are put in a separate report.
|Design Assistant (Elaborated)||Lists Design Assistant rules that failed during the Analysis & Elaboration stage.|
|Design Assistant (Synthesized)||Lists Design Assistant rules that failed during the Synthesis stage.|
Did you find the information on this page useful?