Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Verilog HDL Input Settings (Settings Dialog Box)

Click Assignments > Settings > Verilog HDL Input to specify options for the synthesis of Verilog HDL input files.
Figure 103. Verilog HDL Input Settings Dialog Box
Table 30.  Verilog HDL Input Settings



Verilog Version

Directs synthesis to process Verilog HDL input design files using the specified standard. You can select any of the supported language standards to match your Verilog HDL files or SystemVerilog design files.

Library Mapping File

Allows you to optionally specify a provided Library Mapping File (.lmf) for use in synthesizing Verilog HDL files that contain non-Intel FPGA functions mapped to IP cores. You can specify the full path name of the LMF in the File name box.

Verilog HDL Macro Verilog HDL macros are pre-compiler directives which can be added to Verilog HDL files to define constants, flags, or other features by Name and Setting. Macros that you add appear in the Existing Verilog HDL macro settings list.