2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
2.5.1. Running the Fitter
The Compiler's Fitter module performs all stages of design place and route, including the Plan, Early Place, Place, Route, and Retime stages.
The Intel® Quartus® Prime Pro Edition Compiler allows control and optimization of each individual Fitter stage, including the Plan, Place, and Route stages. Run all stages of the Fitter as part of a full design compilation, or run any Fitter stage independently after design synthesis. Before running the Fitter, you specify settings that impact Fitter processing.
After running a Fitter stage, view detailed report data and analyze the timing of that stage. The Compiler preserves Fitter results of the final snapshot by default.
- Specify initial Fitter constraints:
- To assign device I/O pins, click Assignments > Pin Planner.
- To assign device periphery, clocks, and I/O interfaces, click Tools > Interface Planner .
- To constrain logic placement regions, click Tools > Chip Planner.
- To specify Fitter optimization goals, click Assignments > Settings > Compiler Settings. Compiler Optimization Modes describes these options in detail
- To fine-tune place and route with advanced Fitter options, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)
- To run one or more stages of the Fitter, click any of the following commands on the Compilation Dashboard:
- To run all Fitter stages in sequence, click Fitter.
- To run only device periphery placement and routing, click Plan.
- To run only logic placement, click Place.
- To run only logic routing, click Route.
- To run only retiming of ALM registers into Hyper-Registers, click Retime.2
- To run the Implement flow (runs Plan, Place, Route, and Retime stages), click Fitter (Implement).
- To run the Finalize flow (runs Plan, Place, Route, Retime, and Finalize stages), click Fitter (Finalize).
Disabling or Enabling Physical Synthesis Optimization
2 Retime available for Intel® Hyperflex™ architecture devices only.
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