2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
220.127.116.11. Expand Connections
Expand connections, which was previously supported in the Netlist Viewer, is also supported in the RTL Analyzer and useful when performing filtering. Expand Connections allow you to expand a selected pin and reveal the next connected node.
Note: Before using the Expand Connections feature, disable the Auto-hide Unconnected Pins in the Display settings.
To use this feature, select a pin, right-click and select Expand Connections in the context-sensitive menu, as shown in the following image:
Figure 33. Expand Connections
The logical path from the selected pin to the next connected node is highlighted, as shown in the following image:
Did you find the information on this page useful?