2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
2.6. Incremental Optimization Flow
The Intel® Quartus® Prime Pro Edition software supports incremental optimization at each stage of design compilation. In incremental optimization, you run and optimize each compilation stage independently before running the next compilation module in sequence. The Compiler preserves the results of each stage as a snapshot for analysis. When you make changes to your design or constraints, the Compiler only runs stages impacted by the change. Following synthesis or any Fitter stage, you can view results and perform timing analysis; modify design RTL or Compiler settings as needed; and then re-run synthesis or the Fitter and evaluate the results of these changes. Repeat this process until the module performance meets requirements. This flow maximizes the results at each stage without waiting for full compilation results.
Figure 57. Incremental Optimization Flow
|Fitter Stage||Incremental Optimization|
|Plan||After this stage, you can run post-Plan timing analysis to verify timing constraints, and validate cross-clock timing windows. View the placement and properties of the periphery (I/O).|
|Place||After this stage, validate resource and logic utilization in the Compilation Reports, and review placement of design elements in the Chip Planner.|
|Route||After this stage, perform detailed setup and hold timing closure in the Timing Analyzer, and view routing congestion in the Chip Planner.|
|Retime||After this stage, review the Retiming results in the Fitter report and correct any restrictions limiting further retiming optimization.|
Note: The Compiler saves the planned, placed, routed, and retimed snapshots during full compilation only if you turn on Enable Intermediate Fitter Snapshots (Assignments > Settings > Compiler Settings). You can also run any intermediate Fitter stage independently to generate the snapshot for that stage.
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