2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
184.108.40.206. Fast Forward Details Report
The Fast Forward Details report recommends the design modifications necessary to achieve Fast Forward compilation performance levels. Some recommendations might be functionally impossible or impractical for your design. Consider the recommendations that you can implement in RTL to achieve similar performance improvement.
Click any optimization Step in the report to view the implementation details and performance calculations for that step.
Figure 83. Fast-Forward Details Report
Figure 84. Recommendations for Critical Chain
Right-click any path to locate the critical chain in the Fast Forward Viewer. The Fast Forward Viewer displays a predictive representation of the complete design, after implementation of all Fast Forward recommendations.
Figure 85. Locate Critical Chain in Fast Forward Viewer
Figure 86. Fast Forward Viewer Shows Predictive Results
|Step||Displays the pre-optimized Base Performance fMAX, the recommended Fast Forward optimization steps, and the Fast Forward Limit critical path that prevents further optimization.|
|Fast Forward Optimizations Analyzed||Summarizes the optimizations necessary to implement each optimization step.|
|Estimated Fmax||Specifies the potential fMAX performance if you implement all Fast Forward optimization steps.|
|Optimizations Analyzed For Fast Forward Step||Lists design recommendations hierarchically for the selected Step. Click the text to expand the report and view the clock domain, the affected module, and the bus and bits that require modification.|
|Optimizations Analyzed (Cumulative)||Accumulated list of all design changes necessary to reach the selected Step.|
|Critical Chain at Fast Forward Limit||Displays information about any path that continues to limit Hyper-Retiming even after application of all Fast Forward steps. The critical chain is any path that limits further Hyper-Retiming. Click the Fast Forward Limit step to display this field.|
|Recommendations for Critical Chain||Lists register timing path associated with the retiming limitations. Right-click any path to Locate Critical Chain in Fast Forward Viewer.|
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