Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/19/2022

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Document Table of Contents Applying the SDC-on-RTL Constraints

SDC-on-RTL requires you to perform the DNI-based Analysis and Elaboration on your design before applying the constraints, which means that SDC-on-RTL SDC files are read during elaboration. If you modify the constraints after Analysis and Elaboration, then you must rerun Analysis and Elaboration.

During the Analysis and Elaboration, quartus_syn reads all SDC-on-RTL SDC files and applies constraints to your design netlist. The order in which the files are listed in the QSF defines the reading order. Once this compilation stage completes, you can inspect the constraints in multiple ways. For more information, refer to Inspecting SDC-on-RTL Constraints and Types of SDC Files Used in the Intel Quartus Prime Software.

The constraints are stored in the internal Intel® Quartus® Prime software netlist. As the compilation flow progresses, various compiler optimizations keep the constraint targets updated. This permits a write once, use anywhere methodology for the constraints.

Once you are satisfied with the constraints, you can run Synthesis and Early Timing Analysis stages from the compilation dashboard. Synthesis converts the elaborated netlist into the node netlist for mapping to device resources. When Synthesis runs, you can observe that the SDC constraints are processed and propagated by the Synthesis tool, and eventually, these constraints propagate into the Early Timing Analysis stage.

Figure 37. Post-Elaboration Constraints Compilation Report