ID 683236
Date 12/19/2022
Public

2.3.2.1.3. Inspecting SDC-on-RTL Constraints

You can access SDC-on-RTL constraints in multiple ways in the order of the earliest opportunity in the flow, as described in the following sections:
Note: In all of the methods discussed in this section, the SDC-on-RTL constraints are read-only. You cannot modify the constraints in the compilation flow. You can only change the constraints by changing the source RTL SDC file and reloading it during Analysis and Elaboration.

DNI Tcl Console

The DNI Tcl console allows you to experiment conveniently with targeting constraints and the related syntax. For this beta release, the DNI netlist is read-only when accessed from the Tcl console, and constraint commands are not saved into the design database.

Access the DNI Tcl Console through the command-line interface using the following command:
quartus_syn --dni -s

Once the Analysis & Elaboration compilation stage completes, you can load the project in the console (project_open <project_name>) and load the appropriate DNI netlist checkpoint using the dni::load_design -checkpoint "constrained" command. You can now perform tasks such as:

• Dump constraints using the dni::write_sdc command.
• Run constraint commands that are limited to the local session. For more information, refer to Creating Constraints in SDC-on-RTL SDC Files.

RTL Analyzer

After Analysis and Elaboration, you can invoke the RTL Analyzer (Constrained mode) from the compilation dashboard. The RTL Analyzer GUI allows you to view the constraints on the elaborated design netlist. When you select a netlist object in the semantic viewer, you can view constraints targeting that object in the Property viewer. This helps ensure the constraints target the intended nodes in your RTL.

In the following image, you can observe that the iopll_refclk[1] port has three constraints:

Figure 38. Viewing Constraints in the RTL Analyzer
Note:
• To view the connectivity details, right-click on a port and click Display individual bits.
• You can cross-probe the SDC file by right-clicking on a constraint in the Property viewer and selecting the View in Source option.

Additionally, from the RTL Analyzer menu, you can also launch the Object Constraints dialog box (Tools > Object Constraints to view a list of all constraints:

Figure 39. Object Constraints
Note: The Test SDC button allows you to evaluate an SDC file in the current DNI session, but it does not write back to or modify the netlist in any manner. It is suitable only for testing the syntax in the SDC file. Refrain from using this option to add a new constraint.

Intel® Quartus® Prime Timing Analyzer

The Intel® Quartus® Prime Timing Analyzer uses industry-standard constraint and analysis methodology to report on all data required times, data arrival times, and clock arrival times for all register-to-register, I/O, and asynchronous reset paths in your design. The Timing Analyzer verifies that the required timing relationships are met for your design to function correctly and confirms actual signal arrival times against the constraints you specify. For more information about the Timing Analyzer, refer to the Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer .