Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/19/2022
Document Table of Contents Creating Constraints in SDC-on-RTL SDC Files

SDC 2.1 Compliance

SDC-on-RTL SDCs is an industry-standard to provide constraints targeting your RTL. Target nodes are from the elaborated netlist and aligned closely with your RTL. You can target hierarchical nodes and propagate constraints into the compilation flow through various compilation stages.

Note: The read_sdc command loads SDC-on-RTL SDC files into the Timing Analyzer. Depending on the snapshot you loaded, read_sdc attempts to read other SDCs suitable for that snapshot. For additional information about the types of SDC files used for different use cases, refer to Types of SDC Files Used in the Intel® Quartus® Prime Software.

The Intel® Quartus® Prime software preserves the order of constraints in SDC-on-RTL SDC files. The order in which you list constraints in the SDC file defines the order in which they are loaded in the Intel® Quartus® Prime software.

SDC-on-RTL constraints are designed to support only SDC 2.1-compliant commands. Object accessors, such as get_keepers, get_registers, or get_nodes, are notably absent. The following is the list of supported SDC commands, and you can find more information about them in the TCL Commands and Packages Summary section of the Intel® Quartus® Prime Pro Edition User Guide: Scripting:

  • create_clock
  • create_generated_clock
  • set_input_delay
  • set_output_delay
  • set_false_path
  • set_max_delay
  • set_min_delay
  • set_multicycle_path
  • set_clock_groups
  • set_clock_latency
  • set_clock_uncertainty
Note: Not all of these commands support the full selection of SDC 2.1 arguments because the Timing Analyzer does not support all arguments. If you specify an unsupported argument, these commands issue a warning message and ignore the argument. If you prefer a Tcl error when you encounter a warning in the Timing Analyzer, set the ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS QSF variable to ON.

Identifying Timing Paths

For defining timing paths, use SDC standard accessors, such as get_pins, instead of the Intel® Quartus® Prime software-specific commands, such as get_keepers or get_registers. Intel® recommends using explicit get_<pins|ports|nets> commands when targeting objects. Using bare names can result in unintended targets, and DNI might issue a warning.

Intel® Quartus® Prime Conventional SDC (targets Intel® Quartus® Prime timing graph):
set_false_path -from [get_keepers { reg_A }] -to [get_keepers { reg_B }]
SDC-on-RTL SDC (targets your netlist nodes):
set_false_path -from [get_pins { reg_A|clk }] -to [get_pins { reg_B|d }]
Note: The path must start at the register clk pin to identify the timing path. If your design uses reg_A|d or reg_A|q, the timing path in the Timing Analyzer is invalid, as shown in the Report Exception report:
Status Exception Command From Flag From To Flag To Setup Slack
Complete set_false_path -from

[get_pins{tf_sync[0] |ff_src|clk}]


[get_pins{tf_sync[0] |ff_dst|d}]

Invalid set_false_path -from

[get_pins{tf_sync[2] |ff_src|q}]


[get_pins{tf_sync[2] |ff_dst|d}]

Invalid set_false_path -from

[get_pins{tf_sync[3] |ff_src|d}]


[get_pins{tf_sync[3] |ff_dst|d}]

Note: Netlist targets are case-sensitive. Sometimes, the lower-level module ports are capitalized. In this case, using the -nocase option with the get_<pins|ports|nets> commands ignore the case sensitivity.

Debugging SDC-on-RTL Constraints

There are several ways to debug SDC-on-RTL constraints. For example, you can isolate the exact locations where constraints are used in your design and analyze them in the flow. You can also use compilation reports that report the constraints (see Post-Elaboration Constraints Compilation Report). However, when debugging the constraints, consider the following:

Explicit Errors When Loading Constraints

Errors with reading SDC-on-RTL constraints issue an error message with a command stack showing the line number of the offending command. For example:

You can debug erroneous constraints directly through the DNI Tcl console. You can iterate on issues with initial target resolution or command syntax at this early stage easily, as this is the stage where Intel® Quartus® Prime software loads the SDC-on-RTL SDC files.


In general, it is not possible to directly load SDC-on-RTL constraints in the Timing Analyzer because of the following reasons:

  • The target netlist is different in the elaborated netlist and not the timing netlist. Although there may be some common nodes between the two netlists, both netlists are different.
  • Compliant SDC 2.1 syntax used in SDC-on-RTL can be different from the conventional Quartus SDC commands.

Constraint Behavior and Interpretation Issues

When handling the constraints, ensure the following:

  • Targets and basic syntax are correct (node finding or target acquisition). You can use the RTL Analyzer to find the nodes on the elaborated netlist.
  • Constraints make sense with respect to the timing graph (constraint behavior). You can review this in the Timing Analyzer.

    Examine the SDC-on-RTL constraints conveyed to the Timing Analyzer (import_sdc loads only the SDC-on-RTL commands) from the design netlist. The import_sdc command loads a version of the SDC-on-RTL constraints after propagating through various stages of the compile flow. After this step, the experience is the same as a typical Timing Analyzer session.

Note: Although Intel® does not recommend loading raw SDC-on-RTL SDC files from the Timing Analyzer, you can issue Timing Analyzer-compatible SDC commands using the Timing Analyzer Tcl console to debug your design. By issuing SDC commands directly, you can override SDC-on-RTL constraints and explore the effect of changing the values. However, the changes are valid only for that timing analysis session. For permanent changes, you must update the source SDC-on-RTL SDC file and rerun Analysis and Elaboration.

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