Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/19/2022
Document Table of Contents

2.4. Design Synthesis

Design synthesis is the process that translates design source files into an atom netlist for mapping to device resources. You can specify various settings that affect synthesis processing. The Intel® Quartus® Prime Compiler's Analysis and Synthesis module synthesizes standards-compliant Verilog HDL (.v), VHDL (.vhd), and SystemVerilog (.sv). The Compiler can also synthesize Block Design File (.bdf) schematic files, and the Verilog Quartus Mapping (.vqm) files generated by other EDA tools.

Synthesis examines the logical completeness and consistency of the design, and checks for boundary connectivity and syntax errors. Synthesis also minimizes and optimizes design logic. For example, synthesis infers D flip flops, latches, and state machines from "behavioral" languages, such as Verilog HDL, VHDL, and SystemVerilog. Synthesis may replace operators, such as + or –, with modules from the Intel® Quartus® Prime IP library, when advantageous. During synthesis, the Compiler may change or remove user logic and design nodes. Intel® Quartus® Prime synthesis minimizes gate count, removes redundant logic, and ensures efficient use of device resources.

At the end of synthesis, the Compiler generates an atom netlist. Atom refers to the most basic hardware resource in the FPGA device. Atoms include logic cells organized into look-up tables, D flip flops, I/O pins, block memory resources, DSP blocks, and the connections between the atoms. The atom netlist is a database of the atom elements that design synthesis requires to implement the design in silicon.

Figure 42. Design Synthesis

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