External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022

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Document Table of Contents

3.1. Intel® Agilex™ EMIF Architecture: Introduction

The Intel® Agilex™ EMIF architecture contains many new hardware features designed to meet the high-speed requirements of emerging memory protocols, while consuming the smallest amount of core logic area and power.
Note: The current version of the External Memory Interfaces Intel® Agilex™ FPGA IP supports the DDR4 and QDR-IV memory protocols.

The following are key hardware features of the Intel® Agilex™ EMIF architecture:

Hard Sequencer

The sequencer employs a hard Nios® II processor, and can perform memory calibration for a wide range of protocols. You can share the sequencer among multiple memory interfaces of the same or different protocols, for interfaces placed on the same edge of the FPGA.

Note: You cannot use the hard Nios® II processor for any user applications after calibration is complete.

Hard PHY

The PHY circuitry in Intel® Agilex™ devices is hardened in the silicon, which simplifies the challenges of achieving timing closure and minimizing power consumption.

Hard Memory Controller

The hard memory controller reduces latency and minimizes core logic consumption in the external memory interface. The hard memory controller supports the DDR4 memory protocol.

PHY-Only Mode

Protocols that use a hard controller provide a PHY-only option, which generates only the PHY and sequencer, but not the controller. This PHY-only mode is available if you want to implement your own custom controller in the FPGA fabric, rather than using the hardened controller in the I/O subsystem or the soft controllers.

High-Speed PHY Clock Tree

Dedicated high speed PHY clock networks clock the I/O buffers in Intel® Agilex™ EMIF IP. The PHY clock trees exhibit low jitter and low duty cycle distortion, maximizing the data valid window.

Automatic Clock Phase Alignment

Automatic clock phase alignment circuitry dynamically adjusts the clock phase of core clock networks to match the clock phase of the PHY clock networks. The clock phase alignment circuitry minimizes clock skew that can complicate timing closure in transfers between the FPGA core and the periphery.