External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.9. afi_reset_n for DDR4

AFI reset interface
Table 22.  Interface: afi_reset_nInterface type: Reset Output
Port Name Direction Description
afi_reset_n Output Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion