External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2.12. emif_usr_reset_n for QDR-IV

User clock domain reset interface
Table 51.  Interface: emif_usr_reset_nInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion