External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.6. caltiming1

address=32(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_rd_to_rd 5 0 Read to read command timing on same bank. Read
cfg_t_param_rd_to_rd_diff_chip 11 6 Read to read command timing on different chips. Read
cfg_t_param_rd_to_rd_diff_bg 17 12 Read to read command timing on different chips. Read
cfg_t_param_rd_to_wr 23 18 Write to read command timing on same bank. Read
cfg_t_param_rd_to_wr_diff_chip 29 24 Read to write command timing on different chips Read