External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022

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5.3.4. Editing the ed_sim.v File

  1. In a text editor, open the ed_sim.v file, located in the <example design_path>/sim/ed_sim/sim folder.
  2. Add the following lines to the ed_sim.v file, to include the master test program instance:
    //Edit 1 : To connect local_cal_sucess to ARESETn of AXI4 Master BFM
       	 wire local_cal_success;
      	 //Edit 2 : To include master test program instance
        	master_test_program #(
       	 .AXI4_ADDRESS_WIDTH (33),
        	.AXI4_RDATA_WIDTH (32),
      	  .AXI4_WDATA_WIDTH (32),
      	  .AXI4_ID_WIDTH (18),
      	  .AXI4_USER_WIDTH (8),
      	  .AXI4_REGION_MAP_SIZE (16)) 
       	 u_master (mgc_axi4_master_0.mgc_axi4_master_0);
  3. Connect the local_cal_success of emif_fm_0 to ARESETn of the AXI4 Master BFM. Doing this ensures that the BFM does not begin to issue transactions until after the EMIF calibration is successful.
    Figure 115. Edit at EMIF IP Connection
    Figure 116. Edit at AXI4 Master BFM Connection