External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022

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Document Table of Contents

4.4.9. caltiming4

address=35(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_wr_ap_to_valid 5 0 Write with autoprecharge to valid command timing. Read
cfg_t_param_pch_to_valid 11 6 Precharge to valid command timing. Read
cfg_t_param_pch_all_to_valid 17 12 Precharge all to banks being ready for bank activation command. Read
cfg_starve_limit 25 18 Specifies the number of DRAM burst transactions that an individual transaction allows to reorder ahead of it before its priority is raised in the memory controller. Read
cfg_t_param_pdn_to_valid 31 26 Power down to valid bank command window. Read