External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 12/19/2022

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Document Table of Contents Calibration Algorithms for QDR-IV

Address and Command Deskew

QDR-IV uses the loopback mode for address and command deskew. The FPGA sends address and command signals, and the memory device sends back the address and command signals which it captures, via the read data pin of port A. Each input pin is sampled on both the rising and falling clock edges of input CK/CK#. The output value on the rising edge of output clock QKA/QKA# is the value that was sampled on the rising clock edge of the input clock. The output value on the falling edge of the output clock of QKA/QKA# is the inverted value of what was sampled on the falling edge of the input clock.

By sweeping the output delay on the address and command pins on the FPGA, the algorithm determines the right and left edges of the window, and centers the signal accordingly. Deskew calibration can deskew all synchronous address and command signals,

Figure 66. QDR-IV Address/Command Loopback
Figure 67. QDR-IV Address/Command Deskew – Right Edge Detected
Figure 68. QDR-IV Address/Command Deskew – Left Edge Detected

For more information about loopback mode, refer to your QDR-IV memory device data sheet.