AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

ID 683155
Date 7/08/2015
Public
Document Table of Contents

1.6.14. Overall Summary

It is important to analyze the performance of your PDN design given your specific PCB configuration and FPGA current requirements.

Reductions in the decoupling complexity can be made by using accurate power estimates for your design. Decoupling complexity is dependent on the magnitude of dynamic current, and the dynamic current is a percentage of the IMax. Therefore over estimating the IMax for your design can result in an excessive number of decoupling capacitors.

Decoupling capacitor savings can be made by not over-estimating the FPGA current requirements, or with accurate use of the x or x/related settings in the PDN Tool.

The key to optimizing your PDN design at high-frequencies is to reduce parasitic inductance wherever possible. Increasing power and ground plane pair capacitance also improves high-frequency performance. Reducing effective series resistance can help the PDN performance at low-frequencies. This can be done in the following ways:

  • Reduce the spreading inductance from the power and ground plane pair to the FPGA by increasing the number of power and ground vias connecting the planes to the FPGA.
  • Reduce the vertical loop inductance from the power and ground plane pair to the FPGA by moving them closer to the surface of the PCB that the FPGA is mounted to.
  • Reduce the vertical loop inductance from the decoupling capacitors to the power and ground plane pair by placing them on the surface of the PCB that is closest to the planes.
  • Use VOS with lower mounting inductance (Lmnt) instead of VOE capacitor mounting.
  • Increase inter-plane capacitance of your power and ground plane pair by reducing their dielectric thickness and increasing their surface area.
  • Use ultra-low (Effective Series Resistance) ESR bulk capacitors to help at low frequencies,
  • Consider using larger vias with lower ESL to reduce via loop inductance.
  • Use larger diameter through hole vias for all power connections to reduce via inductance. Micro-vias should not be used for PDN design.
  • Use ultra-low ESL mounting capacitors such as X2Y package styles instead of standard 0603, 0402 or 0201 packages.

By using the Core Clock Frequency and Current Ramp Up Period parameters, it is possible to de-rate the VCC supply at high frequencies and make the VCC supply PDN design easier.

Using the Altera PDN Tool it is possible to assess the effect of each improvement on the PDN design. Each improvement in the PDN performance improves reliability and saves cost through reduced numbers of PCB mounted decoupling capacitors.

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