AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
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Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers

You should use the correct number of power and ground via pairs for your device. This can be found in the device pinout data. This example uses an AX115N_F45 device selection from the PDN Tool and the initial power plane allocation, the Number of Power/Ground Via Pairs and Layer Number data is corrected and entered into the PDN Tool as shown below:

Figure 11. Correct Number of Power/Ground Via Pairs and Layer Number

With the corrected Number of Power/Ground Via Pairs and Layer Number data, the total number of required decoupling capacitors remains at 301 for the VCC, VCCT_GXB and VCCR_GXB supplies. The VCC, VCCT_GXB, and VCCR_GXB Impedance plots are shown below.

Figure 12. VCC, VCCT_GXB, and VCCR_GXB PDN Performance with corrected Number of Power/Ground Via Pairs and Layer Numbers

The following figure shows that the VCC supply Feffective parameter has increased from 10.62MHz to 30.68MHz. The increase in performance is due to an increase in the number of power/ground vias from 50 to 197, and a reduction in spreading inductance (Ls). The vertical loop inductance is reduced by moving the VCC supply plane closer to the FPGA from Layer 18 to Layer 15.

Figure 13.  VCC Supply Feffective with corrected Number of Power/Ground Via Pairs and Layer Numbers

In contrast, the VCCT_GXB and VCCR_GXB supply impedance plots shows a lower frequency Zeffective and Ztarget intersect and hence worse PDN performance. This is because the Number of Power/Ground Via Pairs was corrected from 50 to 16 and the spreading inductance increased. The reduction in performance is despite the planes moving closer to the FPGA from Layer 18 to Layer 9, resulting in a reduction in vertical loop inductance.

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