1.3.2. Clock Frequencies
Dynamic power requirements increase with clock frequency. To account for worst case current requirement conditions, Altera recommends using the highest clock frequencies that your design will run at. When using dynamic reconfiguration of PLLs in your design, ensure that your estimates are based on the highest frequency you intend to use for logic clocked by the PLLs.
For multiple clock frequency domains in your design, it is tempting to simplify your estimates by assuming that all clock domains in your design run at the same highest frequency. Estimate each clock domain separately, because over estimation makes the PDN design difficult. The EPE and Power Analyzer allow you to do this estimation.
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