AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6.13. Overall Design Study Capacitor Savings

This design study demonstrated the following improvements in PDN performance and the reduction in the number of PCB mounted decoupling capacitors.
Table 3.   Study Results showing PDN performance Improvements and reduction in PCB mounted decoupling capacitors

PDN Design Stage

VCC Feffective (MHz)

VCC Caps Required

VCCR_GXB Caps

VCCT_GXB Caps

Original stackup, all supplies on L18, # PWR/GND vias = 50

10.62

>301

>301

>301

Corrected # PWR/GND vias and layer number

Reduced spreading inductance for VCC

Increased spreading inductance for VCCR_GXB & VCCT_GXB

Reduced vertical inductance for VCC, VCCR_GXB, VCCT_GX

30.68

>301

>301

>301

Reduce vertical inductance by moving supplies to more optimal layers closer to the FPGA

35.61

>301

>301

>301

Increase high-frequency capacitance by moving planes closer together

36.71

>301

>301

239

Reduce vertical inductance by placing decoupling capacitors on top surface

36.71

>301

255

180

Reduce capacitor mounting inductance by using low ESL X2Y caps

36.71

>301

28

22

Improve low-frequency performance by using low ESR bulk caps

36.71

>301

23

17

De-rate VCC high-frequency requirement by using the Core Clock Frequency and Current Ramp Up Period parameters

36.71

37

23

17

The diagrams below compare the original (left) and final (right) PDN Tool number of required capacitors for the VCC, VCCT_GXB, and VCCR_GXB supplies.

Figure 28. Comparison of VCC, VCCT_GXB, and VCCR_GXB Supply Required Capacitors Between the Original (Left) and Final (Right) PDN Designs

The diagrams below compare the performance of the original (top row) and final (bottom row) PDN performance of the VCC, VCCT_GXB, and VCCR_GXB supplies.

Figure 29. VCC, VCCT_GXB, VCCR_GXB Supply Performance Comparison Between Original (Top Row), and Final (Bottom Row)
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