AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6.5. Moving Supplies to Optimal Layers

Reducing the spreading inductance (Ls) between the planes and the FPGA increases the effective frequency of the VCC supply. Re-allocating the FPGA supply rails in the layer-stack so that they have lower vertical inductance, will also show an improvement.

Moving the VCCT_GXB and VCCR GXB supplies from Layer 9 to Layer 4, and the VCC supply from Layer 15 to Layer 9, brings them closer to the FPGA with a lower vertical loop inductance.

The following figure shows a comparison between the initial supply layer allocation on the left with the new allocation on the right.

Figure 14. Original Layer Allocation (Left) Versus New Layer Allocation (Right)

As a result of these changes, the PDN Tool reports that the VCC supply Feffective has improved from 30.68MHz to 35.61MHz.

Figure 15. VCC Supply Feffective with Better Supply Plane Allocation

The following figure shows that VCCT_GXB and VCCR_GXB supply impedances are close to meeting the 70MHz target. However, further optimization is required because more than 301 capacitors are still required for each of the three supplies.

Figure 16. VCC, VCCT_GXB, and VCCR_GXB Supply PDN Performance with Better Supply Plane Allocation
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