AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
ID
683155
Date
7/08/2015
Public
1.6.1. Initial Stackup Entry
1.6.2. Using the Correct Number of Power/Ground Via Pairs
1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number
1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers
1.6.5. Moving Supplies to Optimal Layers
1.6.6. Moving Power and Ground Planes Closer Together
1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB
1.6.8. Using X2Y Decoupling Capacitors
1.6.9. Using Ultra–Low ESR Bulk Capacitors
1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4
1.6.11. Assessing How Much Total Capacitance Might be Required
1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters
1.6.13. Overall Design Study Capacitor Savings
1.6.14. Overall Summary
1.6.15. References
1.3.5. Data Patterns
Power requirements depend on toggle % of the logic in your design. A clock-like data pattern has higher current requirements than a PRBS pattern. A PRBS pattern has higher current requirements than those for a grey-code pattern.
Use the highest toggle % that you expect to see in your design. The PDN design becomes difficult if you over estimate. Although it is design dependent, Altera assumes a 12.5% toggle percentage. Use the PPPA to analyze the toggle % of your design.
When using the Quartus PPPA, base your power estimations on simulation-based input data. It provides accurate power estimations.