AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

Download PDF
ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB

In all steps so far, the decoupling capacitors are placed on the bottom surface of the PCB and the FPGA is placed on the top.

Traditionally the decoupling capacitors are placed at the bottom side of the PCB, beneath the FPGA and connect directly to the BGA vias. It is assumed that the best electrical position is the closest physical location to the FPGA pins.

In the layer-stack if the power and ground plane pair are close to the FPGA, the total vertical inductance of the vias between the capacitors and plane, and between the plane and FPGA is less if the decoupling capacitors are placed on the top surface of the PCB.

Assuming wide contiguous power and ground planes that have thin separation, the inductance is much lower even though the physical horizontal distance of the capacitors placed around the outside of the FPGA is far greater.

In this 18 Layer example, the VCCT_GXB, and VCCR_GXB supplies are allocated to layer 4 which is closer to the FPGA than the mid point in the layer-stack. Therefore if the capacitors are placed on the top surface of the PCB, the combined vertical loop inductance between decoupling capacitor to plane, and plane to FPGA is lower.

Providing the PDN Tool with the freedom to place capacitors on either the top or bottom surface of the PCB can be achieved by duplicating entries for select capacitor values. You can allocate one to the top surface, and the other to the bottom surface. This is shown below with the effect that the number of capacitors required for the VCCT_GXB, and VCCR_GXB supplies is reduced to 255 and 180 respectively.

Figure 21. Capacitors Required for the VCC, VCCT_GXB, and VCCR_GXB Supplies After Moving Capacitors to the Top Surface

The target impedance is now met up to 70MHz for the VCCT_GXB, and VCCR_GXB supplies but the large number of high-frequency 22nF capacitors shows there are still challenges in achieving Ztarget at high-frequencies.

Figure 22. VCC, VCCT_GXB, and VCCR_GXB Supply PDN Performance After Moving Capacitors to the Top Surface
Level Two Title