AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

ID 683155
Date 7/08/2015
Public
Document Table of Contents

1.1. Impact of a Poor PDN

A stable power supply is the foundation of your FPGA design. It helps ensure that the device is within electrical specifications. A robust Power Delivery Network (PDN) that manages voltage ripple, is an important part of your power supply design.

With an increase in current loading, an insufficient PDN can result in excessive voltage ripple, voltage drops, and VRM instability. Voltage ripple on VCC supplies can cause brown-out conditions or timing margin reduction through power supply noise induced jitter. This can lead to data integrity problems.

A robust PDN is important for transceiver designs. A transceivers performance can be adversely affected by voltage ripple on its power supplies. Increased voltage ripple on transceiver power supplies can increase the Bit Error Rate (BER) through increased transmit jitter or reduced jitter tolerence.

Jitter induced by supply voltage ripple on General Purpose IO (GPIO) and PLL supplies reduces timing margin on External Memory Interfaces (EMIF) such as DDR3 and DDR4. Bit errors can be seen if timing margins are violated.

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