AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
ID
683155
Date
7/08/2015
Public
1.6.1. Initial Stackup Entry
1.6.2. Using the Correct Number of Power/Ground Via Pairs
1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number
1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers
1.6.5. Moving Supplies to Optimal Layers
1.6.6. Moving Power and Ground Planes Closer Together
1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB
1.6.8. Using X2Y Decoupling Capacitors
1.6.9. Using Ultra–Low ESR Bulk Capacitors
1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4
1.6.11. Assessing How Much Total Capacitance Might be Required
1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters
1.6.13. Overall Design Study Capacitor Savings
1.6.14. Overall Summary
1.6.15. References
1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4
Swapping VCC on Layer 9 with VCCT_GXB and VCCR_GXB on Layer 4 to see the effect of moving the VCC supply closer to the FPGA at the expense of the VCCT_GXB and VCCR_GXB supplies has the effect of improving the VCC Feffective to 38.78MHz. All three supplies now require greater than 301 capacitors so this is not a viable solution because the VCCT_GXB and VCCR_GXB supplies may be insufficiently decoupled. For this design example, we keep VCC on Layer 9, and VCCT_GXB and VCCR_GXB on Layer 4.