F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

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Document Table of Contents

6.1. Top-Level Settings

Table 79.  Top-Level Settings
Parameter Value Default Value Description
Hard IP Mode

Gen4 1x16, Interface - 512-bit

Gen3 1x16, Interface - 512-bit

Gen4 1x8, Interface - 256-bit

Gen3 1x8, Interface - 256-bit

Gen4 2x8, Interface - 256-bit

Gen3 2x8, Interface - 256-bit

Gen4 1x4, Interface - 128-bit

Gen3 1x4, Interface - 128-bit

Gen4 2x4, Interface - 128-bit

Gen3 2x4, Interface - 128-bit

Gen4 4x4, Interface - 128-bit

Gen3 4x4, Interface - 128-bit

Gen4x16, Interface - 512-bit

Select the following elements:

Lane data rate:
  • Gen3 and Gen4 are supported.
Lane width:
  • x16, x8 and x4 modes support both Root Port and Endpoint.
Note: Gen1/Gen2 or lower link width configurations are supported via link down training. Refer to Figure 2 for more detail on the supported configuration modes
Port Mode

Root Port

Native Endpoint

Note: These are the available options when Enable TLP Bypass is set to False. If TLP Bypass mode is enabled, refer to the table Port Mode Options in TLP Bypass below for available port mode options.

Native Endpoint

Specifies the port type.
Enable PMA registers access True/False False Enable the PHY Reconfiguration Interface.
PLD Clock Frequency

500 MHz

400 MHz

350 MHz

250 MHz

500 MHz (for Gen4 modes)

250 MHz (for Gen3 modes)

Select the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen4 modes, the available clock frequencies are 500 MHz / 400 MHz / 350 MHz (for Intel® Agilex™ )

For Gen3 modes, the available clock frequency is 250 MHz (for Intel® Agilex™ and Intel® Stratix® 10 DX).

Enable TLP- Bypass mode True/False False
Enable the TLP Bypass feature.
Note: For configurations where multiple ports are available, it is possible to enable TLP Bypass on a per-port basis.
Enable SRIS Mode True/False False

Enable the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.

Enable CVP (Intel VSEC) True/False False

Enablement of CvP for x16 Core or Port0, single tile only. p0_app_req_retry_en_i signal must be tied tie off to zero when enabling CvP. Refer to Intel Agilex Device Configuration via Protocol (CvP) Implementation User Guide for more details on CvP.

Table 80.  Port Mode Options in TLP Bypass
Configuration Available Port Modes
Port 0 Port 1 Port 2 Port 3
1x16 (Gen4x16 or Gen3x16) TLP-Bypass On: Upstream N/A N/A N/A
TLP-Bypass On: Downstream N/A N/A N/A
2x8 (Gen4x8/Gen4x8 or Gen3x8/Gen3x8) TLP-Bypass On: Upstream TLP-Bypass On: Upstream N/A N/A
TLP-Bypass On: Downstream TLP-Bypass On: Downstream N/A N/A
TLP-Bypass Off: Endpoint TLP-Bypass On: Upstream N/A N/A
TLP-Bypass On: Upstream TLP-Bypass On: Downstream N/A N/A
4x4 (Gen4x8 or Gen3x8) TLP-Bypass On: Upstream TLP-Bypass On: Upstream TLP-Bypass On: Upstream TLP-Bypass On: Upstream
TLP-Bypass On: Downstream TLP-Bypass On: Downstream TLP-Bypass On: Downstream TLP-Bypass On: Downstream

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