F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.4.11.2. ebfm_log_stop_sim Verilog HDL Function

The ebfm_log_stop_sim procedure stops the simulation.

Location

 

Syntax

Verilog HDL: return:=ebfm_log_stop_sim(success);

Argument

success

When set to a 1, this process stops the simulation with a message indicating successful completion. The message is prefixed with SUCCESS.

Otherwise, this process stops the simulation with a message indicating unsuccessful completion. The message is prefixed with FAILURE.

Return

Always 0

This value applies only to the Verilog HDL function.