6.2.5. Configuration, Debug and Extension Options
|Gen 3 Requested equalization far-end TX preset vector||0 - 65535||0x00000200||Specifies the Gen 3 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.|
|Gen 4 Requested equalization far-end TX preset vector||0 - 65535||0x00000080||Specifies the Gen 4 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.|
|Enable RX Buffer Limit Ports||True/False||False||When selected, RX buffer limit ports are exported allowing you to control the buffer limits for RX Posted, Non-Posted and CplD packets. Otherwise, the Maximum Buffer Size is used.|
|Enable HIP dynamic reconfiguration of PCIe* registers||True/False||False||Enable the user Hard IP reconfiguration Avalon® -MM interface.|
|Predetermined number of lanes||
|Maximum link width||
Defines the number of lanes which are connected and good.
Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver.
Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle.
It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 22.214.171.124.1 of the PCI Express Base Specification.
When you have unused lanes in the system, you must change the value in this register to reflect the number of lanes. For instance, if you find that one of the used lanes is bad, then you must reduce the value of "Predetermined number of lanes".
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