F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

Download PDF
ID 683140
Date 10/22/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Introduction 3. IP Architecture and Functional Description 4. Advanced Features 5. Interfaces 6. Parameters 7. Testbench 8. Troubleshooting/Debugging 9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives 10. Revision History of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Implementation of Address Translation Services (ATS) in Endpoint Mode C. Packets Forwarded to the User Application in TLP Bypass Mode D. Root Port Enumeration
2. Introduction x
2.1. Overview 2.2. Features 2.3. Release Information 2.4. Device Family Support 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. IP Architecture and Functional Description x
3.1. Architecture 3.2. Functional Description 3.3. Avalon-ST TX/RX 3.4. Interrupts 3.5. Completion Timeout 3.6. Hot Plug 3.7. Power Management 3.8. Configuration Output Interface (COI) 3.9. Configuration Intercept Interface (EP Only) 3.10. Hard IP Reconfiguration Interface 3.11. PHY Reconfiguration Interface 3.12. Page Request Service (PRS) (EP Only)
3.1. Architecture x
3.1.1. Clocks 3.1.2. Refclk 3.1.3. Reset
3.2. Functional Description x
3.2.1. PMA/PCS 3.2.2. Data Link Layer 3.2.3. Transaction Layer
3.3. Avalon-ST TX/RX x
3.3.1. TLP Header and Data Alignment 3.3.2. Avalon-ST RX 3.3.3. Avalon-ST TX 3.3.4. Tag Allocation 3.3.5. Completion Buffer Size
3.3.2. Avalon-ST RX x
3.3.2.1. RX Flow Control
3.3.3. Avalon-ST TX x
3.3.3.1. TX Flow Control
3.4. Interrupts x
3.4.1. Legacy Interrupts 3.4.2. MSI 3.4.3. MSI-X
3.10. Hard IP Reconfiguration Interface x
3.10.1. Configuration Registers Access
3.10.1. Configuration Registers Access x
3.10.1.1. Direct User Avalon-MM Interface (Byte Access) 3.10.1.2. Debug Register Interface Access (Dword Access)
4. Advanced Features x
4.1. Virtualization Support 4.2. TLP Bypass Mode 4.3. Precision Time Measurement (PTM) 4.4. Scalable IOV
4.1. Virtualization Support x
4.1.1. Single Root I/O Virtualization (SR-IOV) 4.1.2. VirtIO
4.1.1. Single Root I/O Virtualization (SR-IOV) x
4.1.1.1. SR-IOV Implementation
4.1.1.1. SR-IOV Implementation x
4.1.1.1.1. Functional Level Reset (FLR)
4.1.2. VirtIO x
4.1.2.1. VirtIO Implementation 4.1.2.2. VirtIO Registers
5. Interfaces x
5.1. Overview 5.2. Clocks and Resets 5.3. Serial Data Interface 5.4. Avalon-ST Interface 5.5. Interrupt Interface 5.6. Hard IP Status Interface 5.7. Error Interface 5.8. 10-bit Tag Support Interface 5.9. Completion Timeout Interface 5.10. Power Management Interface 5.11. Hot Plug Interface (RP Only) 5.12. Configuration Output Interface 5.13. Configuration Intercept Interface (EP Only) 5.14. Hard IP Reconfiguration Interface 5.15. PHY Reconfiguration Interface 5.16. Page Request Service (PRS) Interface (EP Only) 5.17. FLR Interface Signals 5.18. PTM Interface Signals 5.19. VF Error Flag Interface Signals 5.20. VirtIO PCI Configuration Access Interface Signals
5.4. Avalon-ST Interface x
5.4.1. Avalon-ST RX Interface Signals 5.4.2. Avalon-ST TX Interface Signals
5.5. Interrupt Interface x
5.5.1. Legacy Interrupt Interface Signals 5.5.2. MSI Pending Bits Interface Signals
6. Parameters x
6.1. Top-Level Settings 6.2. Core Parameters
6.2. Core Parameters x
6.2.1. Avalon Parameters 6.2.2. Base Address Registers 6.2.3. PCI Express and PCI Capabilities Parameters 6.2.4. Device Identification Registers 6.2.5. Configuration, Debug and Extension Options
6.2.3. PCI Express and PCI Capabilities Parameters x
6.2.3.1. Device Capabilities 6.2.3.2. Link Capabilities 6.2.3.3. Legacy Interrupt Pin Register 6.2.3.4. MSI Capabilities 6.2.3.5. MSI-X Capabilities 6.2.3.6. Slot Capabilities 6.2.3.7. Latency Tolerance Reporting (LTR) 6.2.3.8. Process Address Space ID (PASID) 6.2.3.9. Device Serial Number Capability 6.2.3.10. Page Request Service (PRS) 6.2.3.11. Access Control Service (ACS) Capabilities 6.2.3.12. Power Management 6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers 6.2.3.14. Precision Time Measurement (PTM) 6.2.3.15. Address Translation Services (ATS) 6.2.3.16. TLP Processing Hints (TPH) 6.2.3.17. VirtIO Parameters
7. Testbench x
7.1. Endpoint Testbench 7.2. Test Driver Module 7.3. Root Port BFM 7.4. BFM Procedures and Functions
7.3. Root Port BFM x
7.3.1. BFM Memory Map 7.3.2. Configuration Space Bus and Device Numbering 7.3.3. Configuration of Root Port and Endpoint 7.3.4. Issuing Read and Write Transactions to the Application Layer
7.4. BFM Procedures and Functions x
7.4.1. ebfm_barwr Procedure 7.4.2. ebfm_barwr_imm Procedure 7.4.3. ebfm_barrd_wait Procedure 7.4.4. ebfm_barrd_nowt Procedure 7.4.5. ebfm_cfgwr_imm_wait Procedure 7.4.6. ebfm_cfgwr_imm_nowt Procedure 7.4.7. ebfm_cfgrd_wait Procedure 7.4.8. ebfm_cfgrd_nowt Procedure 7.4.9. BFM Configuration Procedures 7.4.10. BFM Shared Memory Access Procedures 7.4.11. BFM Log and Message Procedures 7.4.12. Verilog HDL Formatting Functions
7.4.9. BFM Configuration Procedures x
7.4.9.1. ebfm_cfg_rp_ep Procedure 7.4.9.2. ebfm_cfg_decode_bar Procedure
7.4.10. BFM Shared Memory Access Procedures x
7.4.10.1. Shared Memory Constants 7.4.10.2. shmem_write Task 7.4.10.3. shmem_read Function 7.4.10.4. shmem_display Verilog HDL Function 7.4.10.5. shmem_fill Procedure 7.4.10.6. shmem_chk_ok Function
7.4.11. BFM Log and Message Procedures x
7.4.11.1. ebfm_display Verilog HDL Function 7.4.11.2. ebfm_log_stop_sim Verilog HDL Function 7.4.11.3. ebfm_log_set_suppressed_msg_mask Task 7.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 7.4.11.5. ebfm_log_open Verilog HDL Function 7.4.11.6. ebfm_log_close Verilog HDL Function
7.4.12. Verilog HDL Formatting Functions x
7.4.12.1. himage1 7.4.12.2. himage2 7.4.12.3. himage4 7.4.12.4. himage8 7.4.12.5. himage16 7.4.12.6. dimage1 7.4.12.7. dimage2 7.4.12.8. dimage3 7.4.12.9. dimage4 7.4.12.10. dimage5 7.4.12.11. dimage6 7.4.12.12. dimage7
8. Troubleshooting/Debugging x
8.1. Hardware
8.1. Hardware x
8.1.1. Debugging Link Training Issues 8.1.2. Debugging Data Transfer and Performance Issues
8.1.1. Debugging Link Training Issues x
8.1.1.1. Generic Tools and Utilities 8.1.1.2. SignalTapII Logic Analyzer 8.1.1.3. Additional Debug Tools
8.1.1.3. Additional Debug Tools x
8.1.1.3.1. Using the Hard IP Reconfiguration Interface 8.1.1.3.2. Enable and Read LCRC and ECRC Error Count
8.1.2. Debugging Data Transfer and Performance Issues x
8.1.2.1. Advanced Error Reporting (AER) 8.1.2.2. Second-Level Debug Tools
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
B. Implementation of Address Translation Services (ATS) in Endpoint Mode x
B.1. Sending Translated/Untranslated Requests B.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) B.3. Invalidating Requests/Completions
C. Packets Forwarded to the User Application in TLP Bypass Mode x
C.1. EP TLP Bypass Mode (Upstream) C.2. RC TLP Bypass Mode (Downstream)
1. Acronyms
2. Introduction
3. IP Architecture and Functional Description
4. Advanced Features
5. Interfaces
6. Parameters
7. Testbench
8. Troubleshooting/Debugging
9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives
10. Revision History of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Implementation of Address Translation Services (ATS) in Endpoint Mode
C. Packets Forwarded to the User Application in TLP Bypass Mode
D. Root Port Enumeration

5.20. VirtIO PCI Configuration Access Interface Signals

Table 78.  VirtIO PCI Configuration Access Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_virtio_pcicfg_vfaccess_o Output EP coreclkout_hip

Indicates the driver access is to a VF.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_vfnum_o.

p#_virtio_pcicfg_vfnum_o[VFNUM_WIDTH-1:0] Output EP coreclkout_hip

Indicates the corresponding Virtual Function number associated with the current Physical Function that the driver’s write or read access is targeting.

Validated by virtio_pcicfg_vfaccess_o and by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

p#_virtio_pcicfg_pfnum_o[PFNUM_WIDTH-1:0] Output EP coreclkout_hip

Indicates the corresponding Physical Function number that the driver’s write or read access is targeting.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

p#_virtio_pcicfg_bar_o[7:0] Output EP coreclkout_hip

Indicates the BAR holding the PCI configuration access structure. The driver sets the BAR to access by writing to cap.bar.

Values 0x0 to 0x5 specify a BAR belonging to the function located beginning at 10h in the PCI Configuration Space.

The BAR can be either 32-bit or 64-bit. Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_length_o[31:0] Output EP coreclkout_hip

Indicates the length of the structure. The length may include padding, or fields unused by the driver, or future extensions.

The driver sets the size of the access by writing 1, 2 or 4 to cap.length.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_baroffset_o[31:0] Output EP coreclkout_hip

Indicates where the structure begins relative to the base address associated with the BAR. The driver sets the offset within the BAR by writing to cap.offset.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_cfgdata_o[31:0] Output EP coreclkout_hip

Indicates the data for BAR access. The pci_cfg_data will provide a window of size cap.length into the given cap.bar at offset cap.offset. Validated by driver write access to pci_cfg_data. The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_cfgwr_o Output EP coreclkout_hip Indicates driver write access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.
p#_virtio_pcicfg_cfgrd_o Output EP coreclkout_hip

Indicates driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_appvfnum_i[VFNUM_WIDTH-1:0]

Input EP coreclkout_hip

This is a dummy signal created for backward compatibility with P-Tile PCIe Hard IP. It can be safely ignored in new design.

p#_virtio_pcicfg_apppfnum_i[PFNUM_WIDTH-1:0] Input EP coreclkout_hip

This is a dummy signal created for backward compatibility with P-Tile PCIe Hard IP. It can be safely ignored in new design.

p#_virtio_pcicfg_rdack_i Input EP coreclkout_hip

Indicates an application read access data ack to store the config data in pci_cfg_data. User is required to assert rdack on every read access to pci_cfg_data. The corresponding Virtual Function is

identified from the value of virtio_pcicfg_appvfnum_i.
p#_virtio_pcicfg_rdbe_i[3:0] Input EP coreclkout_hip

Indicates application enabled bytes within virtio_pcicfg_data_i.

Validated by virtio_pcicfg_rdack_i.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

p#_virtio_pcicfg_data_i[31:0] Input EP coreclkout_hip

Indicates application data to be stored in PCI Configuration Access data registers.

Validated by virtio_pcicfg_rdack_i and virtio_pcicfg_rdbe_i.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

Level Two Title