F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

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3.3.3.1. TX Flow Control

Before a TLP can be transmitted, flow control logic verifies that the link partner's RX port has sufficient buffer space to accept it. The TX Flow Control interface reports the link partner's available RX buffer space to the Application. It reports the space available in units called Flow Control credits for posted, non-posted and completion TLPs (as defined in the RX Flow Control section).

TX credit limit signals are provided in a TDM manner similar to how the RX credit limit signals are provided.

Figure 24. TX Flow Contrrol TDM Reporting of Credit Limits
Figure 25. Buffer Limits Update example
Note: Above is an example showing TX flow control interface is updated when multiple MWr requests are sent. The tx_cdts_limit_o bus value is incremented when a TLP is acknowledged by the receivers and rolls over when reaching 0xFFFF.

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