F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

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Document Table of Contents

4.1.1.1. SR-IOV Implementation

Accessing VF PCIe Information

The PCIe configuration space for VFs is not directly available to the user application. User application can use the following methods to retrieve necessary information (bus master enable, MSI-X etc.):
  • Monitor specific VF registers using the Configuration Intercept Interface
  • Read/write specific VF registers using the Hard IP Reconfiguration Interface

VF IDs are calculated within F-Tile. User application has sideband signals rx_st_vf_num_o and rx_st_vf_active_o with the TLP to identify the associated VFs within the PFs.

BDF Asssignment

When SR-IOV is enabled, the ARI capability is always enabled.

The F-Tile IP for PCIe automatically calculates the completer/requester ID on the Transmit side. Your application needs to provide the VF and PF information in the Header as shown below: (For x16, sn is either s0 or s1. For x8, sn is s0).
  • tx_st_hdr_sn[127]: must be set to 0
  • tx_st_hdr_sn[83]: tx_st_vf_active
  • tx_st_hdr_sn[82:80]: tx_st_func_num[2:0]
  • tx_st_hdr_sn[95:84]: tx_st_vf_num[11:0]
In the following example, VF3 of PF1 is receiving and sending a request: For the Receive TLP:
  • rx_st_func_num_o = 0x1 indicating that a VF associated with PF1 is making the request.
  • rx_st_vf_num_o = 0x3
  • rx_st_vf_active_o = 1 indicating that VF3 of PF1 is the active VF.
For the Transmit TLP of VF3 associated with PF1:
  • tx_st_hdr_sn[83] = 0x1
  • tx_st_hdr_sn[82:80] = 0x1
  • tx_st_hdr_sn[95:84] = 0x3

VF Error Reporting

The VFs, with no AER support, are required to generate Non-Fatal error messages. The IP does not generate any error message. It is up to the user application logic to generate appropriate messages when specific error conditions occur. The F-Tile IP for PCIe makes necessary signals available to the user application logic to generate these messages. The Completion Timeout Interface and VF Error Flag Interface provide the necessary information to generate Non-Fatal error messages.

VF to PF Mapping

VF to PF mapping always starts from the lowest possible PF number. For instance, if the IP has 2 PFs, wherein PF0 has 64 VFs and PF1 has 16 VFs, VF1 to VF64 are mapped to PF0, and VF65 to VF80 are mapped to PF1.

Currently, the IP core only supports the following PF/VF combinations.

Table 26.  Supported PF/VF Combinations
Number of PFs Number of VFs per PF (PF0/PF1/PF2/PF3/PF4/PF5/PF6/PF7) Total VFs
1 8 8
1 16 16
1 32 32
1 64 64
1 128 128
1 256 256
1 512 512
2 16/16 32
2 32/32 64
2 128/128 256
2 256/256 512
2 32/0 32
2 0/32 32
2 64/0 64
2 0/64 64
2 128/0 128
2 0/128 128
2 256/0 256
2 0/256 256
2 512/0 512
2 0/512 512
2 1024/0 1024
2 0/1024 1024
2 2048/0 2048
2 0/2048 2048
4 128/0/0/0 128
4 0/128/0/0 128
4 256/0/0/0 256
4 0/256/0/0 256
4 1024/0/0/0/0 1024
4 0/1024/0/0 1024
8 256/0/0/0/0/0/0/0 256
8 0/256/0/0/0/0/0/0 256

For example, the row that shows the combination of four PFs, 256 VFs, and the notation 256/0/0/0 in the Number of VFs per PF column indicates that all 256 VFs are mapped to PF0, while no VF is mapped to PF1, PF2 or PF3. SR-IOV permutations allow any PF to be assigned the initial VF allocation.

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