F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.1.2. PCIe Configuration Header Registers

The Corresponding Section in PCIe Specification column in the tables in the Configuration Space Registers section lists the appropriate sections of the PCI Express Base Specification that describe these registers.

Figure 74. PCIe Type 0 Configuration Space Registers - Byte Address Offsets and Layout
Figure 75. PCIe Type 1 Configuration Space Registers - Byte Address Offsets and Layout

Did you find the information on this page useful?

Characters remaining:

Feedback Message