F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.2. Refclk

There are ten reference clock pins for FGT PMAs at the package level. Eight of the FGT reference clocks (refclk[0]-refclk[7]) can be used as reference clock inputs for PCI Express channels. There are up to four reference clock ports (refclk0 – refclk3) in the F-Tile Avalon Streaming IP for PCI Express depending on the Hard IP mode configuration in the IP. For Hard IP modes that span more than one FGT quads, you must use reference clock pins that are accessible by the quads. Depending on the HIP mode, you must assign the reference clock ports of the IP to corresponding reference clock pins in your Intel® Quartus® Prime design.

The table below shows the mapping of reference clock pins to the reference clock ports of the F-Tile Avalon Streaming IP for PCI Express depending on the Hard IP mode.

Table 10.  Reference Clock Port to Reference Clock Pin Mapping
Mode refclk0 port refclk1 port refclk2 port refclk3 port
1 x16 refclk[2] or refclk[3] or refclk[4] or refclk[5] pin refclk[2] or refclk[3] or refclk[4] or refclk[5] pin N/A N/A
1 x8 refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin N/A N/A
2 x8 refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin refclk[2] or refclk[3] or refclk[4] or refclk[5] or refclk[6] or reflck[7] pin N/A N/A
1 x4 refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin N/A N/A
2 x4 refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin N/A N/A
4 x4 refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin refclk[2] or refclk[3] or refclk[4] or refclk[5] or refclk[6] or reflck[7] pin refclk[0] or refclk[1] or refclk[2] or refclk[3] or refclk[4] or reflck[5] pin refclk[2] or refclk[3] or refclk[4] or refclk[5] or refclk[6] or reflck[7] pin
Note:
  1. For 1 x16, 1 x8 and 1 x4 modes, both refclk0 and refclk1 ports need to be connected to a single outrefclk_fgt_i (i = 0 to 7) port from “F-Tile Reference and SystemPLL Clocks” IP.
  2. For 2 x8, 2 x4 and 4 x4 modes, user has an option to share a single refclk source across all the refclk port, connect to a single outrefclk_fgt_i (i = 0 to 7) port from “F-Tile Reference and SystemPLL Clocks” IP.
  3. Independent refclk source is supported for 2 x8 and 4 x4 modes, but not in 2 x4 mode.
Note: For additional information about reference clock pins and reference clock network, refer to the Reference Clock Network section in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
Figure 4. Single 100 MHz Clock Source in 2x8 Mode
Figure 5. Independent 100 MHz Clock Source in 2x8 Mode

In 2x8 mode, you can drive the refclk0 and refclk1 ports with either a single 100 MHz clock source connected to a reference clock pin at package level, or two independent 100 MHz sources depending on your system architecture. For example, if your system has each x8 port connected to a separate CPU/Root Complex, it may be necessary to drive the reference clock pins using independent clock sources. PERST# needs to indicate the stability of the clock source.

Figure 6. Single 100 MHz Clock Sources in 4x4 Mode
Figure 7. Independent 100 MHz Clock Sources in 4x4 Mode

In 4x4 mode, you can drive the refclk0 to refclk3 ports with either a single 100 MHz clock source connect to a reference clock pin at package level, or two independent 100 MHz clock sources or four independent clock sources depending on your system architecture. PERST# needs to indicate the stability of the clock source.

One of the reference clock pins refclk[0] to refclk[7] can also be shared as the 100 MHz reference clock to the System PLL which generates the pld_clk and coreclkout_hip clocks. The reference clock for the System PLL must always be running. If this clock goes down, the PCI Express controllers cannot communicate with the FPGA fabric.

Note: For additional information of restrictions on reference clock and the System PLL, refer to the Clock Rules and Restrictions section in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

Did you find the information on this page useful?

Characters remaining:

Feedback Message