F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

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8.1.1.3.2. Enable and Read LCRC and ECRC Error Count

Table 109.  Address Offsets and Bit Settings to enable and read LCRC and ECRC error count
Offset x16 (Port 0) Offset x8 (Port 1) Offset x4 (Ports 2, 3) Bit Position Register
0x119[0] 0x119[0] 0x00119 [0] Enable CRC Check
0x00340 0x00308 0x002B4 [1:0]

Event counter clear

Set to 2’b01 to clear error counter defined in registers 0x00343 and 0x00342

Set to 2’b11 to clear all error counters

[4:2]

Event counter enable

Set to 3‘b111

0x00341 0x00309 0x002B5 [7:0]

Event counter lane select

Set to x00

0x00342 0x0030A 0x002B6 [7:0]

Event number

For LCRC error count, set to 0x01

For ECRC error count, set to 0x02

0x00343 0x0030B 0x002B7 [7:0]

Group number

For LCRC error count, set to 0x02

For ECRC error count, set to 0x03

000x344 0x0030C 0x002B8 [7:0] Error counter data bit [7:0]
0x00345 0x0030D 0x002B9 [7:0] Error counter data bit [15:8]
0x00346 0x0030E 0x002BA [7:0] Error counter data bit [23:16]
0x00347 0x0030F 0x002BB [7:0] Error counter data bit [31:24]

Follow the steps below to access registers in above table using the Hard IP reconfiguration interface

  1. Enable the Hard IP reconfiguration interface (User Avalon-MM interface) using the IP Parameter Editor.
  2. Enable CRC check by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  3. Set the group number by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  4. Set the event number by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  5. Set the event counter lane select by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  6. Set event counter enable by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  7. Read the error count data by a read operation from the address hip_reconfig_address[20:0].

Example: To read the LCRC error count of x16 Port 0 using the registers

  1. Enable the Hard IP reconfiguration interface (User Avalon-MM interface) using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x000119 to enable CRC check.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x00119
    • p0_hip_reconfig_writedata[7:0] = 8'h01
  3. Perform read-modify-write to address 0x000343 to set Group number.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x00343
    • p0_hip_reconfig_writedata[7:0] = 8'h02
  4. Perform read-modify-write to address 0x000342 to set Event number.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x00342
    • p0_hip_reconfig_writedata[7:0] = 8'h01
  5. Perform read-modify-write to address 0x000341 to set Event counter lane select.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x00341
    • p0_hip_reconfig_writedata[7:0] = 8'h00
  6. Perform read-modify-write to address 0x000340 to set enable event counter.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x00340
    • p0_hip_reconfig_writedata[7:0] = 8'h1C
  7. Read the error counter data by performing a read operation from registers 0x344, 0x345, 0x346, and 0x347.

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