F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/22/2021
Public

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3.10. Hard IP Reconfiguration Interface

The Hard IP reconfiguration interface is an Avalon-MM slave interface with a 21-bit address and an 8-bit data bus. It is also sometimes referred to as the User Avalon-MM Interface. It provides access to the configuration registers and the IP core registers. You can use this interface to dynamically modify the value of configuration registers.
Note: After a warm reset or cold reset, changes made to the configuration registers of the Hard IP via the Hard IP reconfiguration interface are lost as these registers revert back to their default values.

This interface can be used in Endpoint, Root Port and TLP Bypass modes. However, it must be enabled if Root Port or TLP Bypass mode is selected. In Root Port mode, the application logic uses the Hard IP reconfiguration interface to access its PCIe configuration space to perform link control functions (such as Hot Reset, link disable, or link retrain).

In TLP Bypass mode, the Hard IP forwards the received Type0/1 Configuration request TLPs to the application logic, which must respond with Completion TLPs with a status of Successful Completion (SC), Unsupported Request (UR), Configuration Request Retry Status (CRS), or Completer Abort (CA). If a received Configuration request TLP needs to update a PCIe configuration space register, the application logic needs to use the Hard IP reconfiguration interface to access that PCIe configuration space register.

Reading from the Hard IP reconfiguration interface of the F-Tile Avalon-ST IP for PCI Express retrieves the current value at a specific address. Writing to the reconfiguration interface changes the data value at a specific address. It’s recommended that user perform read-modify-writes when writing to a register, because two or more features may share the same reconfiguration address.Read/Write Operations using Hard IP Reconfiguration Interface

Modifying the PCIe configuration registers directly affects the behavior of the PCIe device. This is a per-port interface.

Figure 40. Read/Write Operations using Hard IP Reconfiguration Interface
Table 21.   Address Map for User Avalon-MM Interface
Register Offset Port0 (x16 Core) Port2 (x4 Core_0) Port1 (x8 Core) Port3 (x4 Core_1)
0x0_0000

Physical Function 0 Configuration Register.

Refer to Appendix A for more details of the configuration space.

Physical Function 0 Configuration Register.

Refer to Appendix A for more details of the configuration space.

Physical Function 0 Configuration Register.

Refer to Appendix A for more details of the configuration space.

Physical Function 0 Configuration Register.

Refer to Appendix A for more details of the configuration space.

0x0_1000

Physical Function 1 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 1 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x0_2000

Physical Function 2 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 2 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x0_3000

Physical Function 3 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 3 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x0_4000

Physical Function 4 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 4 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x0_5000

Physical Function 5 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 5 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x0_6000

Physical Function 6 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 6 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x0_7000

Physical Function 7 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA

Physical Function 7 Configuration Register.

Refer to Appendix A for more details of the configuration space.

NA
0x1_4068 User Avalon-MM Control Register User Avalon-MM Control Register User Avalon-MM Control Register User Avalon-MM Control Register
0x1_4200 Debug DBI Register Debug DBI Register Debug DBI Register Debug DBI Register
0x9_0000 Completion timeout Register Completion timeout Register Completion timeout Register Completion timeout Register

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