SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

You will observe some unconstrained clocks from the Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP core if you are using the SDI Multi rate (up to 12G) RX preset with Intel® Arria® 10 or Intel® Cyclone® 10 GX devices.

For example, you may observe the following report in an RX PHY with simplex configuration:

<Rx PHY path …|… 
gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_reg.reg>
To resolve this violation, apply the following constraints in your .sdc file.
  1. Create generated clock name (name this clock).
    create_generated_clock -name (Clock Name, e.g. <Rx PHY path>||rx_clk}
    -source {<Rx PHY path>|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|
    inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_2_reg} \\
        
    -divide_by 2 -multiply_by 1 -duty_cycle 50.00 \\
    
    {<Rx PHY path>|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|
    inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_reg.reg}
    
  2. Set false path.
    set_false_path [get_clocks {<Clock name given in (1), e.g. <Rx PHY path>||rx_clk}]
Note: Refer to the generated .sdc file for the design example provided in the parameter editor: sdi_ii_a10_demo.sdc ( Intel® Arria® 10) or sdi_ii_c10_demo.sdc ( Intel® Cyclone® 10 GX).

Did you find the information on this page useful?

Characters remaining:

Feedback Message