SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3.10. Detect 1 and 1/1.001 Rates

This submodule indicates if the incoming video stream is running at PAL (1) or NTSC (1/1.001) rate. The output port signal, rx_clkout_is_ntsc_paln is set to 0 if the submodule detects the incoming stream as PAL (148.5 MHz or 74.25 MHz recovered clock) and set to 1 if the incoming stream is detected as NTSC (148.35 MHz or 74.175 MHz recovered clock).

For correct video rate detection, you must set the top level port signal, rx_coreclk_is_ntsc_paln, to the following bit:

  • 0 if the rx_coreclk signal is 297 MHz, 148.5 MHz or the rx_coreclk_hd signal is 74.25 MHz
  • 1 if the rx_coreclk signal is 296.7 MHz, 148.35 MHz or the rx_coreclk_hd signal is 74.175 MHz
Note: On Intel® Agilex™ device, the value for Rx core clock (rx_coreclk) frequency parameter in the IP GUI must be set to rx_coreclk's frequency value. The rx_coreclk_is_ntsc_paln signal is deprecated on Intel® Agilex™ device.