SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

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5.3.2. Insert/Check CRC

The HD-SDI can optionally include a line-based CRC code, which makes up two of the EAV extension words as defined in the SMPTE ST 292 specification.

This submodule calculates the CRC based on the LFSR approach in the SMPTE specification. Note that you can configure this submodule to either insert or check the CRC.

For the transmitter, the core formats and inserts the CRC into two CRC EAV extension words—CRC0 and CRC1. For correct CRC generation and insertion, assert the tx_trs signal for the first word of both EAV and SAV TRS as shown in the Line Number Insertion timing diagram. Perform CRC insertion only when the top level port, tx_enable_crc, is set to logic 1.

For the receiver, the core checks the CRC against the value of CRC0 and CRC1 that appear in the incoming stream. If there is a mismatch between the locally calculated value and the value in the stream, this submodule indicates an error.

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