SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6. SDI II IP Core Signals

The following tables list the SDI II IP core signals by components.

  • Protocol blocks—transmitter, receiver
  • Transceiver blocks—PHY management, PHY adapter, Native PHY IP
Note: These signals are applicable for all supported Intel FPGA devices unless specified otherwise.

Did you find the information on this page useful?

Characters remaining:

Feedback Message